Prefetchers are used to fetch program instructions and program data so that a processor can readily avail itself of the retrieved information as it is needed. The prefetcher predicts which instructions and data the processor might use in the future so that the processor need not wait for the instructions or data to be accessed from system memory, which typically operates at a slower rate than the processor. With a prefetcher implemented between a processor and system memory, the processor is less likely to remain idle as it waits for requested data from memory. As such, prefetchers generally improve processor performance.
Generally, the more predictions generated by a prefetcher, the more likely that the prefetcher can arrange to have the necessary instructions and data available for a processor, thereby decreasing the latency of a processor. But many conventional prefetchers lack capabilities to manage predictions after they are generated and before a processor requests those predictions. Usually these prefetchers store prefetch data in a single cache memory, which is typically lacking in functionality to limit predictions that are superfluous with respect to those already stored in the cache. Moreover, cache memories of traditional prefetchers are not sufficiently designed for managing predicted addresses stored therein as they are for merely storing data generally.
In view of the foregoing, it would be desirable to provide a system, an apparatus and a method for minimizing the drawbacks of managing predictive accesses to memory, especially from the time when a prefetcher generates predictions to when a processor requests those predictions.